In digital communications systems it is often advantageous to embed a client signal for transport in a wrapper 10 (see FIG. 1), which is a repetitive frame format of fixed length and repetition rate. The wrapper 10 is also referred to herein as a “frame”. Often, it is advantageous for the wrapper 10 to have a frequency that is not locked (is asynchronous or plesiochronous) to the embedded client signal. Furthermore, it is sometimes advantageous to maintain, at the client egress, the exact bit rate that the client had upon ingress. Such a relationship can be required, for example, when the exact bit sequence is replicated from ingress to egress.
Such systems use a constant bit rate (CBR) mapping scheme that allows for the mapping of arbitrary client protocols into the wrapper 10. The wrapper 10 is generated with the aid of a free-running read clock 12 that is shown, for example, in FIG. 2. The read clock 12 can be a free-running oscillator and is independent of the input client signal. The wrapper 10 consists of an overhead section 14, and a payload section 15 having multiple client data sections 16 (three being shown and designated by reference numerals 16a, 16b and 16c by way of example), one or more variable stuff section(s) 17, and one or more fixed stuff sections 18 (three being shown and designated by reference numerals 18a, 18b, and 18c by way of example). The lengths of the variable stuff sections 17 and fixed-stuff sections 18 are client specific and are chosen such that a wrapper payload bandwidth is roughly equivalent to that of the client. The payload section 15 of the wrapper 10 consists of N groups for client data, and each variable stuff section 17 may be used to transport client data.
However, even with the fixed stuffing, the mapping of the client signal to the payload section 15 is not exact and “asynchronous mapping” may be used. In asynchronous mapping, there are, in addition to the client data sections 16, the variable stuff sections 17 that contain, or do not contain, client data in a given wrapper 10. By variably ‘stuffing’ (inserting null data) in these variable stuff sections 17 or inserting actual client data, the client signal may be transported in a bit-for-bit transparent manner, and the ingress and egress client frequencies are exactly the same, when measured over the long term. The variable stuff sections 17 are often called “justification opportunities” and the terms “variable stuff sections” and “justification opportunities” are used interchangeably herein. In a given wrapper 10, it must be signaled from the transmitter to the receiver whether or not each justification opportunity 17 carries data or stuffing. The signaling is accomplished with the aid of one or more bits in the overhead section 14.
FIG. 2 shows a typical asynchronous mapping system 30 for decoding and encoding client data. The asynchronous mapping system 30 includes a client receive circuit 32, a First-in, First-out (FIFO) memory 34 and a frame transmit circuit 36. The client receive circuit 32 includes a clock and data recovery circuit 40, a FIFO write clock 42 and a serial-to-parallel converter 44. The client data is received by the clock and data recovery circuit 40, and forwards serial data to the serial-to-parallel converter 44, which converts the serial data to a series of parallel n-bit words. This is done to limit the rate at which an individual data signal can be toggled, such that the data processing can be performed in a low-cost, high-density logic device, for example, CMOS. Each n-bit word is entered into the (FIFO) memory 34. The FIFO write clock 42 is derived from the client clock decoded by the clock and data recovery circuit 40, divided by n, where n is the parallel data width.
The frame transmit circuit 36 includes a framer 50, a parallel to serial converter 52, the free-running read clock 12, and a justification control logic 56. The wrapper 10 to be transmitted is constructed by the framer 50 that is synchronous with the wrapper clock, which may be driven by the free-running read clock 12. A wrapper data source, per n-bit wrapper word is selected by the framer 50. For fixed client data locations, the data is derived from the FIFO memory 34. For justification opportunities 17, the wrapper data is derived from either the FIFO memory 34 or a stuff value, depending upon a FIFO fill level of the FIFO memory 34. If the FIFO fill level is above a threshold, the framer 50 may place data in the justification opportunity 17. When the FIFO fill level is below a threshold, the framer 50 may stuff the justification opportunity 17 with null data. The FIFO fill level is monitored by the justification control logic 56. Data indicative of justification control is also inserted in the overhead section 14 of the wrapper 10 in order to inform an edge node 60 (see FIG. 3) whether each justification opportunity 17 contains data or stuffing.
FIG. 3 shows a client decapsulation circuit 61 running on the edge node 60 for providing client data into a client network. Again, for efficiency the received signal is converted to a parallel n-bit wide data path (it is not necessary that the receiver data path width match the transmitter data path width) by the serial to parallel converter 44. The edge node 60 distinguishes client data (including justification opportunities 17) within the wrapper 10 and stores the client data only in the FIFO memory 34. Separately, the clock and data recovery circuit 40 of the edge node 60 synthesizes a client clock by processing a received wrapper clock, fixed client data locations, and the justification control channel. The client decapsulation circuit 61 also includes a client clock synthesis circuit 66 that reads data from the decoded wrapper 10 indicative of the justification opportunity 17 and uses such data to regenerate or synthesize the client clock, which is referred to herein as a regenerated egress client clock. Signals indicative of the regenerated egress client clock are provided to a client framer 67 which functions to form the wrapper 10 with the client data and transmit the wrapper 10 to a parallel to serial converter 68. The parallel to serial converter 68 converts the wrapper 10 into a serial form and then provides the converted wrapper 10 to the client's network.
Often it is desired to pass a given client signal that is encoded in the above manner through a series of one or more intermediate nodes, wherein each intermediate node generates a wrapper 10 that is plesiochronous with the other wrappers 10. As before, each wrapper 10 may contain more than one client signal, and at each intermediate node, the multiple clients may be switched and combined in different wrappers 10. At each such intermediate node, the client data must be recovered from the upstream node wrapper and re-encoded downstream to the next node. The client phase information must likewise be recovered and re-encoded.
In the bit-for-bit transmission of client signals, it is often advantageous or even required to minimize the generation of jitter and wander via the overall transmission processes. Jitter and wander generation represent a deviation in time from the temporal position of each transmitted bit or symbol at which it was received at the client ingress (neglecting a fixed transport delay). Frequency components of this deviation above 10 Hz are termed “jitter” and components below 10 Hz are termed “wander”. For example, minimal jitter and wander generation is required for the transmission of client signals using SONET/SDH.
As described above, the conventional method for making the justification decision relies on sampling a current FIFO fill level 69 (or the amount of client data stored in the FIFO memory 34) at fixed intervals. The FIFO memory 34 is instantaneously sampled immediately before the justification opportunity 17 in the wrapper 10 and compared to a minimum threshold 72. Since the frame format is fixed, sample points 70a, 70b and 70c occur at fixed intervals with respect to the operating clock frequency as shown in FIG. 4.
The FIFO fill level 69 at any given moment is a function of the real-time performance of the client receive circuit 32 and the frame transmit circuit 36. The client receive circuit 32 and the frame transmit circuit 36 can be viewed as ON/OFF processes. Consider for example FIG. 5, when the client receive circuit 32 is writing client data into the FIFO memory 34 and the frame transmit circuit 36 is not reading; during such periods the FIFO fill level 69 of the FIFO memory 34 will naturally grow in length. The relative speed at which the client receive circuit 32 inputs data into the FIFO memory 34 and the frame transmit circuit 36 removes data from the FIFO memory 34 creates variations in the FIFO fill level 69 of the FIFO memory 34. The ON/OFF signature depends on the format of the frame.
Given the plesiochronous nature of the write and read clocks 42 and 12, both the write clock 42 and the read clock 12 operate at the same nominal frequency with only a slight frequency mismatch. Therefore, the operating frequency of one wrapper 10 will always be slightly faster than the other. This mismatch is generally quantified in units of parts per million. Unlike FIG. 4 above, the sample point at which the justification decision is made will vary from one frame to the next. This is illustrated in FIG. 6. It should be evident that the sample point will cycle though the entire wrapper 10 and how quickly it cycles depends directly on the parts per million differences.
The problem with this approach lies in the fact that the justification opportunities 17 will mimic the behavior of the FIFO memory 34. This is illustrated in FIG. 7. During a first epoch (E1), each instantaneous sample obtained during consecutive frame periods shows the FIFO fill level 69 to be below the minimum threshold, therefore, a larger number of the justification opportunities 17 are stuffed with null data. Note that an epoch here consists of one or more consecutive frame periods. During a next epoch (E2), the point has shifted such that each instantaneous sample is above the minimum threshold. Naturally, the framer 50 responds by reducing the number of justification opportunities 17 stuffed with null data. Since the signature of the justification opportunities 17 is instrumental in tuning the regenerated egress client clock, such variations can induce undesirable low-frequency wander in the regenerated egress client clock.
In a concatenated series of nodes, it is possible for any wander generated by the encoding/decoding process to be cumulative. Hence, it is increasingly important to diminish or mitigate the amount of wander generated by each decoding/encoding process to achieve a given net result.
It is evident from the discussion above that the conventional approach to making justification decisions is prone to introducing unwanted wander in the regenerated egress client clock.
Thus there is a need to diminish or mitigate the amount of unwanted wander generated by each decoding/encoding process by the regenerated egress client clock. It is to this problem that the present disclosure is directed to solving.